An electrically erasable and programmable flash memory can preserve data without any power supply. Especially, having a string structure by which a plurality of flash memory cells are connected in series, a NAND-type flash memory can be useful in low-power, e.g. portable, products and can be manufactured at low cost. For these reasons, the NAND-type flash memory devices are in widespread use in various portable products.
Users gradually demand increased memory device functionality. One such demand is increased data input/output rate. This can be realized by increasing page size (or page depth) and memory block size. A page means a bundle of memory cells which are simultaneously selected when one word line is activated, and becomes a basic unit when read/program operations are executed. The memory block comprises multiple pages, and becomes a basic unit when an erase operation is executed.
FIG. 1 is a block diagram that illustrates a conventional NAND-type flash memory device. A NAND-type flash memory device includes a memory cell array 10, a row selecting circuit (or a row decoder circuit) 12, a page buffer circuit (or a data sensing and latching circuit) 14, and a column decoder circuit 16. The memory cell array 10 comprises a plurality of memory blocks BLK0˜BLKn (where n is positive number), and each memory block includes a plurality of strings. As shown in FIG. 1, each string comprises a string selecting transistor SST connected to a corresponding bit line (for example, BL0), a ground selecting transistor GST connected to a common source line CSL, and memory cells MC15˜MC0 which are connected between the string and ground selecting transistors SST and GST in series. The string selecting transistor SST, the memory cells MC15˜MC0, and the ground selecting transistor GST are connected to a string selecting line SSL, word lines WL15˜WL0 and a ground selecting line GSL, respectively. The signal lines SSL, WL15˜WL0, GSL are electrically connected to signal lines SS, Si15˜Si0, GS through corresponding block selecting transistors BS17˜BS0. The block selecting transistors BS17˜BS0 are controlled by a block selecting signal BS in common.
In continuous operation, a row selecting circuit 12 selects any one word line (or page) out of the word lines WL0˜WL15 through the block selecting transistors BS0˜BS17. The page buffer circuit 14 temporarily stores data to be stored in the memory cells of a selected page, or senses data stored in the memory cells of the selected page. The page buffer circuit 14 comprises columns related to the selected page, i.e. it comprises a plurality of page buffers which correspond to bit lines.
For example, as shown in FIG. 2, each page buffer can comprise a PMOS transistor M1 operating as a power supply, an NMOS transistor M2 operating as a pass transistor, inverters INV1 and INV2 forming a latch, and NMOS transistors M3 and M4 for controlling the latch. In the page buffer, data sensed from a corresponding memory cell during a read operation are loaded to a latch node ND_LAT, and other data to be stored (or programmed) in a corresponding memory cell during a program operation are loaded thereto. A detailed operation of the page buffer is disclosed in U.S. Pat. No. 5,712,818 entitled: “Data Loading Circuit For Parallel Program Of Nonvolatile Semiconductor Memory”.
The data bits sensed from the memory cells of the selected page will be outputted, to a data bus or other external device, by a predetermined unit (e, g. a byte unit including 8 bits) through the column decoder circuit 16. FIG. 3 illustrates a part of a column decoder circuit according to a conventional technology. The circuit of FIG. 3 corresponds to one data line, and circuits of the same structure would be provided to correspond to other data lines. In FIG. 3, a notation “ND_LAT” indicates the latch node of the page buffer illustrated in FIG. 2. First selecting signals YA0˜YA15 are sequentially activated and, substantially simultaneously, second signals YB0˜YB15 are sequentially activated. For example, while each of the second selecting signals YB0˜YB15 is activated, the first selecting signals YA0˜YA15 are sequentially activated. Thus, as known from this structure and control manner, one data bit DL0 is selected out of 256 latched data bits ND_LAT0˜ND_LAT255.
The page size and the block size typically are fixed in hardware when a flash memory is designed. Unlike a NOR-type flash memory, where data are randomly read out by a byte ×8 unit or a word ×16 unit, the NAND-type flash memory senses and latches data by a page unit over a relatively long time (for example, ˜10 μs) by using the page buffer circuit 14. The latched data are sequentially fetched by the by the byte (×8) unit by toggling an nREx pin by an information processing system (e.g. a CPU). Thus, the NAND-type flash memory exhibits a relatively long latency when data are read out. On the contrary, once data are sensed and latched by a page buffer circuit, the NAND-type flash memory data output rate that is substantially higher.
The page size is on an increasing upward trend due to demand by users who want to increase data input/output rates. Such demand is explained by the following. Suppose that there are products having page sizes of 512 bytes (one speed), 1K bytes (double speed), and 2K bytes (quadruple speed). Under this supposition, when data of 8K bytes are sequentially read out, a product having the quadruple speed needs four read operations, another product having the double speed needs eight read operations, and still another product having the one speed needs sixteen read operations. As the page size decreases further, the time required for read/program operations continues to increase.
But as the page size is increased, the following problems arise. As is well known, the program/erase operations include a verify operation in order to determine whether a memory cell is normally programmed/erased. During the verify operation, memory cells of a selected page, i.e. bit lines, are sequentially scanned. This is also called “a verify scanning or column scanning operation.”
In case of the erase operation, since the erase operation is executed for a relatively long time (for example, ˜2 ms), generally, erase time is not limited by the time required for the column scanning operation. In the case of the page program, since the program operation is executed for a relatively short time (for example, ˜240 μs), the time required for the column scanning operation (hereinafter, “column scanning time”) cannot be neglected. Additionally, since the page program includes an algorithm for preventing the problem of excessively programmed memory cells, the column scanning time cannot be further neglected.
Consequently, as the page size is increased due to user demand, the column scanning time will increase in proportion to the increase in the page size. For example, if a period of a clock signal inputted in the column address counter is 50 ns and data latched in the page buffer circuit are pass/fail checked by a byte unit, the column scanning time of the one speed product is about 25 μs (50 ns×512) while that of the quadruple speed product is about 100 μs (50 ns×512×4). Thus, in conventional memory designs, NAND-type flash memory devices present a problem: the column scanning time increases as the page size increases.